[RISCV] Disable EEW=64 for index values when XLEN=32.
authorjacquesguan <jacquesguan@me.com>
Thu, 22 Jul 2021 03:40:31 +0000 (11:40 +0800)
committerjacquesguan <jacquesguan@me.com>
Mon, 10 Jan 2022 02:51:27 +0000 (10:51 +0800)
commit6b8362eb8dc87be8977e3c1d3a7b2ff35a15898c
treefeb82157a1cb5d4b132f7843a7a7253bf95bbe8c
parent6fab2742758197949d7bc624f453e544129709a3
[RISCV] Disable EEW=64 for index values when XLEN=32.

Disable EEW=64 for vector index load/store when XLEN=32.

Differential Revision: https://reviews.llvm.org/D106518
18 files changed:
clang/include/clang/Basic/riscv_vector.td
clang/utils/TableGen/RISCVVEmitter.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll
llvm/test/MC/RISCV/rvv/invalid-eew.s [new file with mode: 0644]