perf/x86/amd: Support PERF_SAMPLE_{WEIGHT|WEIGHT_STRUCT}
authorRavi Bangoria <ravi.bangoria@amd.com>
Wed, 28 Sep 2022 09:57:54 +0000 (15:27 +0530)
committerPeter Zijlstra <peterz@infradead.org>
Thu, 29 Sep 2022 10:20:55 +0000 (12:20 +0200)
commit6b2ae4952ef8ac23b467bc10776404092b581143
tree210d6dfacc49a8f743e10205ec2b567de2d52ea5
parent7c10dd0a88b1cc6ae4637fffb494c5e080027eb6
perf/x86/amd: Support PERF_SAMPLE_{WEIGHT|WEIGHT_STRUCT}

IbsDcMissLat indicates the number of clock cycles from when a miss is
detected in the data cache to when the data was delivered to the core.
Similarly, IbsTagToRetCtr provides number of cycles from when the op
was tagged to when the op was retired. Consider these fields for
sample->weight.

Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20220928095805.596-5-ravi.bangoria@amd.com
arch/x86/events/amd/ibs.c