board: ti: DRA72: revC evm: Update sdram timing configuration for SR2.0
authorRavi Babu <ravibabu@ti.com>
Tue, 15 Mar 2016 23:09:14 +0000 (18:09 -0500)
committerTom Rini <trini@konsulko.com>
Sun, 27 Mar 2016 13:12:14 +0000 (09:12 -0400)
commit6b1c14bb67b261be3b4045e8ce124314a2720ec5
treea6437c10a20ac1e0bfef9ef24e8af6e5953ab398
parent9c90f5135e25a4f9bea5862fd22372b037c80600
board: ti: DRA72: revC evm: Update sdram timing configuration for SR2.0

DDR configuration has changes from SR1.1 based Rev-A/B version of evm
to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher
density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB.

Update the DDR configuration based on data from EMIF configuration
tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the
configuration.

Tested-by: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
board/ti/dra7xx/evm.c