[opcodes, ARM, 14/16] Add mode availability to coprocessor table entries

[opcodes, ARM, 14/16] Add mode availability to coprocessor table entries

The coprocessor_opcodes table is used both to share commonalities in coprocessor-related instructions and to avoid duplication between Arm and Thumb mode. However, some instructions do have differences between Arm and Thumb. For instance, vldmia allows PC as base register in Arm mode but not in Thumb mode.

In that very case the distinction becomes necessary because the encoding with PC as base register is used in Thumb mode to denote a VSCCLRM. It is thus necessary to distinguish what is Arm or Thumb only from what is shared. This patch adds an extra field to the coprocessor_opcodes table entries to indicate what mode is a given instruction available in. The print_insn_coprocessor then uses that field to determine if an entry that matched the mark and value checked should be allowed to match or not given the current mode.

ChangeLog entry is as follows:

*** opcodes/ChangeLog ***

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (enum isa): New enum.
	(struct sopcode32): New structure.
	(coprocessor_opcodes): change type of entries to struct sopcode32 and
	set isa field of all current entries to ANY.
	(print_insn_coprocessor): Change type of insn to struct sopcode32.
	Only match an entry if its isa field allows the current mode.