drm/i915/csr: use intel_de_*() functions for register access
authorJani Nikula <jani.nikula@intel.com>
Fri, 14 Feb 2020 14:09:09 +0000 (16:09 +0200)
committerJani Nikula <jani.nikula@intel.com>
Tue, 18 Feb 2020 08:43:32 +0000 (10:43 +0200)
commit6ae5d1cec102c664831233d726ebcbd6a99813c0
tree86318d869a380c5d3dc85db77d29cd77e7b431ec
parent8d6cae6fcde8dcac3009175b157a79e86c43f5a1
drm/i915/csr: use intel_de_*() functions for register access

The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().

Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().

No functional changes.

Generated using the following semantic patch:

@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)

@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200214140910.23194-1-jani.nikula@intel.com
drivers/gpu/drm/i915/display/intel_csr.c