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(parent: 540dcf1) | patch
fsl-ddr: Fix two bugs in the ddr infrastructure
authorDave Liu <daveliu@freescale.com>
Sat, 14 Mar 2009 04:48:19 +0000 (12:48 +0800)
committerKumar Gala <galak@kernel.crashing.org>
Mon, 30 Mar 2009 18:33:50 +0000 (13:33 -0500)
commit6a8197836702991468cead5ead073f589e2623ad
treeda8979bf71471ade2083ad1a352a32f74a7234c4tree | snapshot
parent540dcf1cb86961e11aa92c47671f27762c581d8ccommit | diff
fsl-ddr: Fix two bugs in the ddr infrastructure

1. wr_lat
   UM said the total write latency for DDR2 is equal to
   WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1.
   so, the WR_LAT = CL - 1;
2. rd_to_pre
   we missed to add the ADD_LAT for DDR2 case.

Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Dave Liu <daveliu@freescale.com>
cpu/mpc8xxx/ddr/ctrl_regs.c diff | blob | history
Domain: System / Kernel;