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[PowerPC] Enhance the selection(ISD::VSELECT) of vector type
authorZi Xuan Wu <wuzish@cn.ibm.com>
Wed, 14 Nov 2018 02:34:45 +0000 (02:34 +0000)
committerZi Xuan Wu <wuzish@cn.ibm.com>
Wed, 14 Nov 2018 02:34:45 +0000 (02:34 +0000)
commit6a3c279d1cdcd4205a233952b4bacd5941cd355e
tree88d06c85528e336e0701b7776a6e592b09a177a5tree | snapshot
parent41390b47de8b8e9952cf466d8220c17ec1bbc326commit | diff
[PowerPC] Enhance the selection(ISD::VSELECT) of vector type

To make ISD::VSELECT available(legal) so long as there are altivec instruction, otherwise it's default behavior is expanding,
which is legalized at type-legalization phase. Use xxsel to match vselect if vsx is open, or use vsel.

Differential Revision: https://reviews.llvm.org/D49531

llvm-svn: 346824
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff | blob | history
llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff | blob | history
llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff | blob | history
llvm/lib/Target/PowerPC/PPCInstrVSX.td diff | blob | history
llvm/test/CodeGen/PowerPC/vec_select.ll diff | blob | history
Domain: System / Toolchain;