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[AMDGPU] Disable the scalar IR, SDWA and load store vectorizer passes at -O1
authorBaptiste Saleil <baptiste.saleil@amd.com>
Tue, 4 May 2021 20:30:56 +0000 (16:30 -0400)
committerBaptiste Saleil <baptiste.saleil@amd.com>
Tue, 4 May 2021 20:44:39 +0000 (16:44 -0400)
commit6a17609157196878b9cd9aa9ce71bde247ca14db
treeb04b4e748bc53b7d548d04b982dc22add92c50d0tree | snapshot
parent17f2d1cb9b93d336d4187cd14307bef1ab535808commit | diff
[AMDGPU] Disable the scalar IR, SDWA and load store vectorizer passes at -O1

This patch disables some of the passes at -O1. These passes have a significant
impact on compilation time, so we only want them to be enabled starting from -O2.

Differential Revision: https://reviews.llvm.org/D101414
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp diff | blob | history
llvm/test/CodeGen/AMDGPU/llc-pipeline.ll [new file with mode: 0644] blob
Domain: System / Toolchain;