drm: rcar-du: Restrict DPLL duty cycle workaround to H3 ES1.x
authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tue, 20 Jun 2017 19:35:44 +0000 (22:35 +0300)
committerLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Thu, 3 Aug 2017 13:17:23 +0000 (16:17 +0300)
commit6a00a4221a9af8117c5fc1d7e2740614bb7626f7
tree9d0ad159fd53b69bc379a7fa7328967bca7cd368
parent3e81374e2014c42abff62cb74b654c6d4fb269ee
drm: rcar-du: Restrict DPLL duty cycle workaround to H3 ES1.x

The H3 ES1.x exhibits dot clock duty cycle stability issues. We can work
around them by configuring the DPLL to twice the desired frequency,
coupled with a /2 post-divider. This isn't needed on other SoCs and
breaks HDMI output on M3-W for a currently unknown reason, so restrict
the workaround to H3 ES1.x.

From an implementation point of view, move work around handling outside
of the rcar_du_dpll_divider() function by requesting a x2 DPLL output
frequency explicitly. The existing post-divider calculation mechanism
will then take care of dividing the clock by two automatically.

While at it, print a more useful debugging message to ease debugging
clock rate issues.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
drivers/gpu/drm/rcar-du/rcar_du_crtc.c