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(parent: 9c978dd) | patch
[RISCV] Add intrinsics for vsetvli instruction
authorCraig Topper <craig.topper@sifive.com>
Fri, 18 Dec 2020 20:08:27 +0000 (12:08 -0800)
committerCraig Topper <craig.topper@sifive.com>
Fri, 18 Dec 2020 20:10:09 +0000 (12:10 -0800)
commit69c8d121f7f22e483e35a3d893052011ee70c23e
tree01bec0472e529624700befe30c30ad1455ccc860tree | snapshot
parent9c978dd6e12e5ffaf5441f459db47e9892b09a82commit | diff
[RISCV] Add intrinsics for vsetvli instruction

This patch adds two IR intrinsics for vsetvli instruction. One to set the vector length to a user specified value and one to set it to vlmax. The vlmax uses the X0 source register encoding.

Clang builtins will follow in a separate patch

Differential Revision: https://reviews.llvm.org/D92973
llvm/include/llvm/IR/IntrinsicsRISCV.td diff | blob | history
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp diff | blob | history
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp diff | blob | history
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h diff | blob | history
llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll [new file with mode: 0644] blob
Domain: System / Toolchain;