PCI/DPC: Fix control register setting
authorKeith Busch <keith.busch@intel.com>
Fri, 28 Apr 2017 16:02:49 +0000 (12:02 -0400)
committerBjorn Helgaas <bhelgaas@google.com>
Mon, 22 May 2017 23:42:44 +0000 (18:42 -0500)
commit69a3025def543b66a9610c86706eebb6b160d3b8
treee621e68777b6ef6e7209a245d746ce6838dcac24
parent993d668183fa49b63939a4f62a558d487fd50c22
PCI/DPC: Fix control register setting

This driver was OR'ing desired bits from the existing control setting.
That could create an invalid DPC Trigger Enabled configuration if the
platform previously set this to "ERR_FATAL", 01b.  The driver currently
wants to set this to ERR_NONFATAL/ERR_FATAL, 10b, and the logical OR of
this gets 11b, which is reserved.  Fix that by masking off the fields it is
setting.

Signed-off-by: Keith Busch <keith.busch@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
drivers/pci/pcie/pcie-dpc.c