phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC
authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Sat, 14 Jan 2023 07:10:05 +0000 (12:40 +0530)
committerVinod Koul <vkoul@kernel.org>
Tue, 17 Jan 2023 06:24:57 +0000 (11:54 +0530)
commit692b65516080302c2782bb7bae12e086f137313d
treed5e4d993833ef6feea0d0a972193a2a9c04c66f8
parentf89dcb24e2ec7edc80f2f56dfa8b3fd22f311561
phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC

UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the
required register settings using the tables_hs_g4 struct instance. This
also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-9-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c