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(parent: 8dcc7e6) | patch
clk: sunxi: Add Allwinner A80 CLK driver
authorJagan Teki <jagan@amarulasolutions.com>
Fri, 11 Jan 2019 10:11:46 +0000 (15:41 +0530)
committerJagan Teki <jagan@amarulasolutions.com>
Fri, 18 Jan 2019 16:49:09 +0000 (22:19 +0530)
commit6901aab8e35183115ae65362f3af0ea095b6c1b8
tree771d46ec8bbb1700ff392289d9a3b2fef9fd4b6etree | snapshot
parent8dcc7e69224f898272dbbbba2d9a1c5efaa28304commit | diff
clk: sunxi: Add Allwinner A80 CLK driver

Add initial clock driver for Allwinner A80.

- Implement UART bus clocks via ccu_clk_gate table for
  A80, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for A80,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
drivers/clk/sunxi/Kconfig diff | blob | history
drivers/clk/sunxi/Makefile diff | blob | history
drivers/clk/sunxi/clk_a80.c [new file with mode: 0644] blob
Domain: System / Kernel;