drm/amd/display: Take FEC Overhead into Timeslot Calculation
authorFangzhi Zuo <Jerry.Zuo@amd.com>
Wed, 1 Mar 2023 02:34:58 +0000 (21:34 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 29 Mar 2023 21:21:06 +0000 (17:21 -0400)
commit68dc1846c3a44d5e633be145c169ce2fd5420695
treea91aa1da086d83359c0a82e3b64009e01173c125
parentf4f3b7dedbe849e780c779ba67365bb1db0d8637
drm/amd/display: Take FEC Overhead into Timeslot Calculation

8b/10b encoding needs to add 3% fec overhead into the pbn.
In the Synapcis Cascaded MST hub, the first stage MST branch device
needs the information to determine the timeslot count for the
second stage MST branch device. Missing this overhead will leads to
insufficient timeslot allocation.

Cc: stable@vger.kernel.org
Cc: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h