clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clk
authorBoris Brezillon <boris.brezillon@free-electrons.com>
Thu, 1 Dec 2016 19:27:21 +0000 (20:27 +0100)
committerStephen Boyd <sboyd@codeaurora.org>
Thu, 8 Dec 2016 22:55:04 +0000 (14:55 -0800)
commit68af4fa8f39b542a6cde7ac19518d88e9b3099dc
treebeb0bea999031d0dcd4729dd6307e9d48ca4c33c
parent035cd485a47dda64f25ccf8a90b11a07d0b7aa7a
clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clk

bcm2835_pll_divider_off() is resetting the divider field in the A2W reg
to zero when disabling the clock.

Make sure we preserve this value by reading the previous a2w_reg value
first and ORing the result with A2W_PLL_CHANNEL_DISABLE.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: <stable@vger.kernel.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/bcm/clk-bcm2835.c