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arm64: dts: imx8qxp: support scu mailbox channel
authorPeng Fan <peng.fan@nxp.com>
Tue, 14 Apr 2020 13:24:28 +0000 (21:24 +0800)
committerShawn Guo <shawnguo@kernel.org>
Tue, 28 Apr 2020 08:50:00 +0000 (16:50 +0800)
commit6895681132ec9d0dda9e95a9ddde3ba59720c1d6
treec216e42eea11bc906b8d88667ba4dc87e63a5d1dtree | snapshot
parent30cdd62dce6b59692a3a9081ab8116a0da07ede4commit | diff
arm64: dts: imx8qxp: support scu mailbox channel

With mailbox driver support i.MX8 SCU MU channel, we could
use it to avoid trigger interrupts for each TR/RR registers
in one MU, instead, only one RX interrupt for a recv and
one TX interrupt for a send.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm64/boot/dts/freescale/imx8qxp.dtsi diff | blob | history
Domain: System / Kernel;