lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Sat, 10 Dec 2022 10:30:09 +0000 (10:30 +0000)
committerAnup Patel <anup@brainfault.org>
Mon, 12 Dec 2022 13:20:46 +0000 (18:50 +0530)
commit684090272af9ce84ff0768d8294bf7d42f14edeb
tree26d2b0d6c57e4ef71fd7360338a5bd5dcf674b21
parent0021b437377b4ea95f567f91fbf506c0b0b9e227
lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100

Add compatible string for Andestech NCEPLIC100 found on Renesas RZ/Five SoC
which is equipped with AX45MP AndesCore.

While at it drop the comma after the sentinel as it does not make sense to
have a comma after a sentinel, as any new elements must be added before the
sentinel.

dts example (Single-core AX45MP):

    soc: soc {
          ....
          plic: interrupt-controller@12c00000 {
              compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
              #interrupt-cells = <2>;
              #address-cells = <0>;
              riscv,ndev = <511>;
              interrupt-controller;
              reg = <0x0 0x12c00000 0 0x400000>;
              clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
              power-domains = <&cpg>;
              resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
              interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
          };
          ....
    };

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
lib/utils/irqchip/fdt_irqchip_plic.c