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[PowerPC] Fix td pattern for P10 VSLDBI and VSRDBI
authorQuinn Pham <Quinn.Pham@ibm.com>
Thu, 16 Sep 2021 19:00:01 +0000 (14:00 -0500)
committerQuinn Pham <Quinn.Pham@ibm.com>
Mon, 27 Sep 2021 17:36:18 +0000 (12:36 -0500)
commit682e15f371db9b515d95fe9571983f1070bbc805
tree61eb1b1b8c289847fdfe72a3064336fb4f9a298atree | snapshot
parentc4afb5f81b62b903e4af8a92235e1b901e184040commit | diff
[PowerPC] Fix td pattern for P10 VSLDBI and VSRDBI

This patch fixes the pattern for the P10 instructions Vector Shift Left
Double by Bit Immediate VN-form and Vector Shift Right Double by Bit
Immediate VN-form. The third argument should be a target constant (`timm`)
instead of an `i32` because an immediate is expected.

Reviewed By: lei

Differential Revision: https://reviews.llvm.org/D109920
llvm/lib/Target/PowerPC/PPCInstrPrefix.td diff | blob | history
Domain: System / Toolchain;