i2c: cadence: Set the hardware time-out register to maximum value
authorVishnu Motghare <vishnum@xilinx.com>
Wed, 3 Dec 2014 12:35:25 +0000 (18:05 +0530)
committerWolfram Sang <wsa@the-dreams.de>
Thu, 4 Dec 2014 18:25:41 +0000 (19:25 +0100)
commit681d15a0f527af7ab3a783e1037de86fbcb136ac
tree72dd858a8368d675e085bcf5a4828a45660d0958
parent9ea359f7314132cbcb5a502d2d8ef095be1f45e4
i2c: cadence: Set the hardware time-out register to maximum value

Cadence I2C controller has bug wherein it generates invalid read transactions
after timeout in master receiver mode. This driver does not use the HW
timeout and this interrupt is disabled but the feature itself cannot be
disabled. Hence, this patch writes the maximum value (0xFF) to this register.
This is one of the workarounds to this bug and it will not avoid the issue
completely but reduces the chances of error.

Signed-off-by: Vishnu Motghare <vishnum@xilinx.com>
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Cc: stable@kernel.org
drivers/i2c/busses/i2c-cadence.c