Workaround ICE9 A1 chip LL bug (MIPS)
authorIvan Maidanski <ivmai@mail.ru>
Wed, 30 Nov 2011 11:37:53 +0000 (15:37 +0400)
committerIvan Maidanski <ivmai@mail.ru>
Wed, 30 Nov 2011 11:37:53 +0000 (15:37 +0400)
commit680314ae8f0ad438b5c4f75d7d84c0907824ab78
treeb42583b55cde024a31e33377b03975fff2477884
parent15df68acc8c3ab899a165837c4d474293699eddb
Workaround ICE9 A1 chip LL bug (MIPS)

* src/atomic_ops/sysdeps/gcc/mips.h (AO_MIPS_LL_FIX): New macro (used
to workaround LL bug in some chips); test AO_ICE9A1_LLSC_WAR new macro.
* src/atomic_ops/sysdeps/gcc/mips.h (AO_fetch_and_add,
AO_test_and_set, AO_compare_and_swap, AO_fetch_compare_and_swap):
Insert AO_MIPS_LL_FIX after every "ll" operation.
src/atomic_ops/sysdeps/gcc/mips.h