gpu: host1x: Support 40-bit addressing
authorThierry Reding <treding@nvidia.com>
Fri, 1 Feb 2019 13:28:25 +0000 (14:28 +0100)
committerThierry Reding <treding@nvidia.com>
Thu, 7 Feb 2019 17:28:35 +0000 (18:28 +0100)
commit67a82dbc0a374df7a348cc8fb28982945035bd25
tree92fa1607b4b4e341508dd3d65c9e74908c04c35a
parent5a5fccbd8c315c08db01e585e1cbe88e30b70691
gpu: host1x: Support 40-bit addressing

Tegra186 and later support 40 bits of address space. Additional
registers need to be programmed to store the full 40 bits of push
buffer addresses.

Since command stream gathers can also reside in buffers in a 40-bit
address space, a new variant of the GATHER opcode is also introduced.
It takes two parameters: the first parameter contains the lower 32
bits of the address and the second parameter contains bits 32 to 39.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/host1x/hw/cdma_hw.c
drivers/gpu/host1x/hw/channel_hw.c
drivers/gpu/host1x/hw/host1x06_hardware.h
drivers/gpu/host1x/hw/host1x07_hardware.h