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(parent: bba6676) | patch
mips: implement MB and WMB
authorJames Cowgill <james410@cowgill.org.uk>
Thu, 4 May 2017 13:32:46 +0000 (14:32 +0100)
committerJames Cowgill <james410@cowgill.org.uk>
Fri, 5 May 2017 16:14:03 +0000 (17:14 +0100)
commit67836c2ab48a5d6a8cd227358fa67e2a260eba34
tree0a723d2d1a0e5bb4044043a5723685071873ebb0tree | snapshot
parentbba6676803e574d433661d6ff35af8095299d024commit | diff
mips: implement MB and WMB

The MIPS architecture has weak memory ordering and therefore requires
sutible memory barriers when doing lock free programming with multiple
threads (just like ARM does). This commit implements those barriers for
MIPS and MIPS64 using GCC bultins which is probably easiest way.
common_mips.h diff | blob | history
common_mips64.h diff | blob | history
Domain: Machine Learning / ML Framework;