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(parent: d5c152c) | patch
memory: tegra: Correct num_tlb_lines for tegra210
authorNicolin Chen <nicoleotsuka@gmail.com>
Thu, 17 Sep 2020 11:31:55 +0000 (04:31 -0700)
committerJoerg Roedel <jroedel@suse.de>
Fri, 18 Sep 2020 09:07:07 +0000 (11:07 +0200)
commit675d12acb66bb190d32a3fae187e379f01cbd8ce
treebfa799b0d6499d932ca5bc68dc04f75c5b553ea7tree | snapshot
parentd5c152c3409ac1982a9277d8d344e073eda17e78commit | diff
memory: tegra: Correct num_tlb_lines for tegra210

According to Tegra210 TRM, the default value of TLB_ACTIVE_LINES
field of register MC_SMMU_TLB_CONFIG_0 is 0x30. So num_tlb_lines
should be 48 (0x30) rather than 32 (0x20).

Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20200917113155.13438-3-nicoleotsuka@gmail.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
drivers/memory/tegra/tegra210.c diff | blob | history
Domain: System / Kernel;