ARM: DRA7: Change configuration to prevent DDR reset control from EMIF
authorNishanth Menon <nm@ti.com>
Tue, 16 Jun 2015 13:29:01 +0000 (08:29 -0500)
committerTom Rini <trini@konsulko.com>
Fri, 19 Jun 2015 20:46:48 +0000 (16:46 -0400)
commit67055bee25c2add9cece7ceb9967bb67df806529
tree1be0f70b0e08d5f5b1b0d5150f1d767242f2cc6b
parent3683c3d1f784d1e81e31066cecefd320b4ffaed4
ARM: DRA7: Change configuration to prevent DDR reset control from EMIF

DRA7/AM57xx devices can be operated in many different configurations.
When the SoC is supposed to support a configuration where low power mode
state may involve the SoC completely powered off and DDR is in self
refresh, SoC EMIF controller should not be the master of the reset
signal and an external entity might be in control of things.

The default configuration of Linux on TI evms involve not powering off
the voltage rails (due to various reasons including reliability concerns)
and must not allow DDR reset to be controlled by EMIF. On platforms
where external entity might control the reset signal, this configuration
will be a "dont care".

Fixes: 536d87470869 ("ARM: DRA7: Update DDR IO registers")
Tested-by: Keerthy <j-keerthy@ti.com>
Acked-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
arch/arm/cpu/armv7/omap5/hw_data.c