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[RISCV] Assemble/Disassemble v-ext instructions.
authorHsiangkai Wang <kai.wang@sifive.com>
Thu, 24 Oct 2019 04:29:28 +0000 (12:29 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Sat, 27 Jun 2020 16:54:07 +0000 (00:54 +0800)
commit66da87dcbaf91fa3393ce80c687e9c2d133ee3ca
treeab4493a7f138a368e9d80411eb36060866d1b4e6tree | snapshot
parentf0634100cdc832605bff355330d2ccdb7f43842fcommit | diff
[RISCV] Assemble/Disassemble v-ext instructions.

Assemble/disassemble RISC-V V extension instructions according to
latest version spec in https://github.com/riscv/riscv-v-spec/.

I have tested this patch using GNU toolchain. The encoding is aligned
to GNU assembler output. In this patch, there is a test case for each
instruction at least.

The V register definition is just for assemble/disassemble. Its type
is not important in this stage. I think it will be reviewed and modified
as we want to do codegen for scalable vector types.

This patch does not include Zvamo, Zvlsseg, and Zvediv.

Differential revision: https://reviews.llvm.org/D69987
51 files changed:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp diff | blob | history
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp diff | blob | history
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp diff | blob | history
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h diff | blob | history
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCV.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrFormats.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrFormatsV.td [new file with mode: 0644] blob
llvm/lib/Target/RISCV/RISCVInstrInfo.h diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfo.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoV.td [new file with mode: 0644] blob
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVRegisterInfo.td diff | blob | history
llvm/lib/Target/RISCV/RISCVSchedRocket32.td diff | blob | history
llvm/lib/Target/RISCV/RISCVSchedRocket64.td diff | blob | history
llvm/lib/Target/RISCV/RISCVSubtarget.h diff | blob | history
llvm/lib/Target/RISCV/RISCVSystemOperands.td diff | blob | history
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h diff | blob | history
llvm/test/MC/RISCV/rvv/add.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/and.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/clip.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/compare.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/convert.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/div.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/fadd.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/fcompare.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/fdiv.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/fmacc.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/fminmax.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/fmul.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/fmv.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/fothers.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/freduction.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/fsub.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/load.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/macc.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/mask.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/minmax.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/mul.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/mv.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/or.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/others.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/reduction.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/shift.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/sign-injection.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/snippet.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/store.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/sub.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/vsetvl.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvv/xor.s [new file with mode: 0644] blob
Domain: System / Toolchain;