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(parent: c28bbd9) | patch
[RISCV] Implement vsoxseg/vsuxseg intrinsics.
authorHsiangkai Wang <kai.wang@sifive.com>
Tue, 19 Jan 2021 02:47:44 +0000 (10:47 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Sat, 23 Jan 2021 00:54:56 +0000 (08:54 +0800)
commit66a49aef690cb2980152d3cfa867e797bbda54be
tree375a6959e52a8da552d664e16a9ee8b8cc08d558tree | snapshot
parentc28bbd97a15d1942ba63998e7ba8609cc87b38aecommit | diff
[RISCV] Implement vsoxseg/vsuxseg intrinsics.

Define vsoxseg/vsuxseg intrinsics and pseudo instructions.
Lower vsoxseg/vsuxseg intrinsics to pseudo instructions in RISCVDAGToDAGISel.

Differential Revision: https://reviews.llvm.org/D94940
llvm/include/llvm/IR/IntrinsicsRISCV.td diff | blob | history
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td diff | blob | history
Domain: System / Toolchain;