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MIPS: uaccess: emulate Ingenic LXW/LXH/LXHU uaccess
authorSiarhei Volkau <lis8215@gmail.com>
Sun, 4 Jun 2023 12:26:52 +0000 (14:26 +0200)
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>
Fri, 9 Jun 2023 07:54:17 +0000 (09:54 +0200)
commit6673c2763f6f999fc32cff1833c7d4d6d35f787b
tree4aa5c4647d327aa6dbbba9be82080a78daca5118tree | snapshot
parent1e13da548fbffb807633df85a244b70caa90bdf7commit | diff
MIPS: uaccess: emulate Ingenic LXW/LXH/LXHU uaccess

The LXW, LXH, LXHU opcodes are part of the MXU ASE found in Ingenic
XBurst based SoCs.

While technically part of the MXU ASE, they do not touch any of the SIMD
registers, and can be used even when the MXU ASE is disabled.

This patch makes it possible to emulate unaligned access for those
instructions.

Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
arch/mips/include/uapi/asm/inst.h diff | blob | history
arch/mips/kernel/unaligned.c diff | blob | history
Domain: System / Kernel;