drm/i915: Add some CHV DPIO lane power state asserts
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 8 Jul 2015 20:46:00 +0000 (23:46 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 1 Sep 2015 09:44:41 +0000 (11:44 +0200)
commit6669e39f95b5530ca8cb9137703ceb5e83e5d648
treed090c4e7f784fbfb3afb3e7a2030437ac85bde82
parenta8f327fb8464875e5b764008a1c50dbc0b384c17
drm/i915: Add some CHV DPIO lane power state asserts

Add some checks that the state of the DPIO lanes is more or less what we
expect based on the overrides.

The hardware only provides two bits per channel indicating whether all
or some of the lanes are powered down, so we can't do an exact check.

Additionally, CL2 powering down before we can check it adds another
twist. To work around this we simply check for the 0 value of the
CL2 register (which is what we get when it's powered down) and
adjust our expectations.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_runtime_pm.c