[DAGCombiner] enable vector transforms for any/all {sign} bits set/clear
authorSanjay Patel <spatel@rotateright.com>
Sat, 1 Apr 2017 15:05:54 +0000 (15:05 +0000)
committerSanjay Patel <spatel@rotateright.com>
Sat, 1 Apr 2017 15:05:54 +0000 (15:05 +0000)
commit665021e7ee2faad573840b7698ad1419aa2fcd92
tree0f9b6c9e2a6a5496d3a1fdeef3654a7bfb34c306
parentfe9340c1682dbce08e6bb1f8720ba89ec495f377
[DAGCombiner] enable vector transforms for any/all {sign} bits set/clear

The code already allowed vector types in via "isInteger" (which might want
a more specific name), so use splat-friendly constant predicates to match
those types.

llvm-svn: 299304
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/PowerPC/setcc-logic.ll
llvm/test/CodeGen/X86/setcc-logic.ll