This patch adds support for the vector quadword add/sub instructions introduced
authorKit Barton <kbarton@ca.ibm.com>
Mon, 25 May 2015 15:49:26 +0000 (15:49 +0000)
committerKit Barton <kbarton@ca.ibm.com>
Mon, 25 May 2015 15:49:26 +0000 (15:49 +0000)
commit6646033e6e759657b6122fde64844fd28a2c9635
treeb29623a45a12224714ae003592cb553300c8a875
parentb028cc80989ccbdeb6940d89b1bac5a036377249
This patch adds support for the vector quadword add/sub instructions introduced
in POWER8:

vadduqm
vaddeuqm
vaddcuq
vaddecuq
vsubuqm
vsubeuqm
vsubcuq
vsubecuq
In addition to adding the instructions themselves, it also adds support for the
v1i128 type for intrinsics (Intrinsics.td, Function.cpp, and
IntrinsicEmitter.cpp).

http://reviews.llvm.org/D9081

llvm-svn: 238144
llvm/include/llvm/IR/Intrinsics.td
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/IR/Function.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll
llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll [new file with mode: 0644]
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
llvm/utils/TableGen/IntrinsicEmitter.cpp