drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores
authorHeiko Stuebner <heiko@sntech.de>
Tue, 11 Oct 2022 23:18:41 +0000 (01:18 +0200)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 27 Oct 2022 21:35:20 +0000 (14:35 -0700)
commit65e9fb081877a18c432c6ff344937b7277c044b5
tree26a5470b97356f9b5e29f5fb4dfc34ef703af484
parent5e9c68ea777594a2d63fa44c0509782e90821707
drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores

With the T-HEAD C9XX cores being designed before or during the ratification
to the SSCOFPMF extension, it implements functionality very similar but
not equal to it.

It implements overflow handling and also some privilege-mode filtering.
While SSCOFPMF supports this for all modes, the C9XX only implements the
filtering for M-mode and S-mode but not user-mode.

So add some adaptions to allow the C9XX to still handle
its PMU through the regular SBI PMU interface instead of defining new
interfaces or drivers.

To work properly, this requires a matching change in SBI, though the actual
interface between kernel and SBI does not change.

The main differences are a the overflow CSR and irq number.

As the reading of the overflow-csr is in the hot-path during irq handling,
use an errata and alternatives to not introduce new conditionals there.

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/all/20221011231841.2951264-2-heiko@sntech.de/
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/Kconfig.erratas
arch/riscv/errata/thead/errata.c
arch/riscv/include/asm/errata_list.h
drivers/perf/riscv_pmu_sbi.c