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(parent: 5dd6bd9) | patch
[RISCV] Codegen support for RV32F floating point comparison operations
authorAlex Bradbury <asb@lowrisc.org>
Wed, 21 Mar 2018 15:11:02 +0000 (15:11 +0000)
committerAlex Bradbury <asb@lowrisc.org>
Wed, 21 Mar 2018 15:11:02 +0000 (15:11 +0000)
commit65d6ea5e68dd5c44f39567f923820d2aef9d41b7
tree7955e8dece5ee775ca697279f37bbe287353f947tree | snapshot
parent5dd6bd9631935f22711e633a936f489ebd9274c4commit | diff
[RISCV] Codegen support for RV32F floating point comparison operations

This patch also includes extensive tests targeted at select and br+fcmp IR
inputs. A sequence of br+fcmp required support for FPR32 registers to be added
to RISCVInstrInfo::storeRegToStackSlot and
RISCVInstrInfo::loadRegFromStackSlot.

llvm-svn: 328104
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfo.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoF.td diff | blob | history
llvm/test/CodeGen/RISCV/bare-select.ll diff | blob | history
llvm/test/CodeGen/RISCV/float-br-fcmp.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/float-fcmp.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/float-select-fcmp.ll [new file with mode: 0644] blob
Domain: System / Toolchain;