PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize
authorqizhong cheng <qizhong.cheng@mediatek.com>
Mon, 27 Dec 2021 13:31:10 +0000 (21:31 +0800)
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Fri, 7 Jan 2022 10:21:51 +0000 (10:21 +0000)
commit65ace9a85fa7f88aec4d9d842061108161fa47bc
tree75b76b6d1bbfa80991bd0dbff0c7ca13d8d13afd
parentfa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf
PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize

Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
be delayed 100ms (TPVPERL) for the power and clock to become stable.

Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Pali Rohár <pali@kernel.org>
drivers/pci/controller/pcie-mediatek.c