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[AArch64] Add asm aliases for MOV, LDR, STR with predicate-as-counter
authorCaroline Concatto <caroline.concatto@arm.com>
Wed, 22 Mar 2023 14:57:18 +0000 (14:57 +0000)
committerCaroline Concatto <caroline.concatto@arm.com>
Wed, 22 Mar 2023 16:05:10 +0000 (16:05 +0000)
commit65890469cebb675e9fa0271dc1ab3b1da15df302
tree963e5df5c8c1941ac52f84ffe443a658f9452b35tree | snapshot
parent06f16232b1b0028ac87d584883bc32220882c73acommit | diff
[AArch64] Add asm aliases for MOV, LDR, STR with predicate-as-counter

In the 2022-12 release of the A64 ISA it was updated that the assembler must
also accept predicate-as-counter register names for the source predicate
register and the destination predicate register for:
 * *MOV: Move predicate (unpredicated)*
 * *LDR (predicate): Load predicate register*
 * *STR (predicate): Store predicate register*

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D146311
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td diff | blob | history
llvm/lib/Target/AArch64/SVEInstrFormats.td diff | blob | history
llvm/test/MC/AArch64/SVE/pfalse.s diff | blob | history
llvm/test/MC/AArch64/SVE/predicate-as-counter-aliases.s [new file with mode: 0644] blob
Domain: System / Toolchain;