[AArch64][SVE] Add DAG combine rules for gather loads and sext/zext
authorAndrzej Warzynski <andrzej.warzynski@arm.com>
Mon, 25 Nov 2019 13:54:47 +0000 (13:54 +0000)
committerAndrzej Warzynski <andrzej.warzynski@arm.com>
Wed, 11 Dec 2019 12:56:18 +0000 (12:56 +0000)
commit65651f197a2c5a7b62f67619c169d2af616a81c6
treef63c96fa0e4c20734eec6b42633de798c7ea37a0
parentcb30ad728f0b7666691c72a6a1399f36ebc60ad5
[AArch64][SVE] Add DAG combine rules for gather loads and sext/zext

Summary:
These changes allow us to support sign-extending gather loads with the
exisiting intrinsics (i.e. @llvm.aarch64.sve.ld1.gather.*).

Reviewers: sdesmalen, huntergr, kmclaughlin, efriedma, rengolin, rovka, dancgr, mgudim

Reviewed By: sdesmalen

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential revision: https://reviews.llvm.org/D70812
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll [new file with mode: 0644]
llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-32bit-scaled-offsets.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-32bit-unscaled-offsets.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-scaled-offset.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-unscaled-offset.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-vector-base.ll