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author	Phoebe Wang <phoebe.wang@intel.com>
	Fri, 17 Jun 2022 13:09:19 +0000 (21:09 +0800)
committer	Phoebe Wang <phoebe.wang@intel.com>
	Fri, 17 Jun 2022 13:34:05 +0000 (21:34 +0800)
commit	655ba9c8a1d22075443711cc749f0b032e07adee
tree	60918da3d9b295e77bf3b5c5261867cd1baf4cfa	tree \| snapshot
parent	6d5d8b131300284d5c26f73017da612db532dc9a	commit \| diff

Reland "Reland "Reland "Reland "[X86][RFC] Enable `_Float16` type support on X86 following the psABI""""

This resolves problems reported in commit 1a20252978c76cf2518aa45b175a9e5d6d36c4f0.
1. Promote to float lowering for nodes XINT_TO_FP
2. Bail out f16 from shuffle combine due to vector type is not legal in the version

50 files changed:

llvm/docs/ReleaseNotes.rst		diff \| blob \| history
llvm/lib/Target/X86/X86FastISel.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86ISelLowering.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86ISelLowering.h		diff \| blob \| history
llvm/lib/Target/X86/X86InstrAVX512.td		diff \| blob \| history
llvm/lib/Target/X86/X86InstrCompiler.td		diff \| blob \| history
llvm/lib/Target/X86/X86InstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86InstrSSE.td		diff \| blob \| history
llvm/lib/Target/X86/X86InstrVecCompiler.td		diff \| blob \| history
llvm/lib/Target/X86/X86InstructionSelector.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86RegisterInfo.td		diff \| blob \| history
llvm/test/Analysis/CostModel/X86/fptoi_sat.ll		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir		diff \| blob \| history
llvm/test/CodeGen/X86/atomic-non-integer.ll		diff \| blob \| history
llvm/test/CodeGen/X86/avx512-insert-extract.ll		diff \| blob \| history
llvm/test/CodeGen/X86/avx512-masked_memop-16-8.ll		diff \| blob \| history
llvm/test/CodeGen/X86/avx512fp16-fp-logic.ll		diff \| blob \| history
llvm/test/CodeGen/X86/callbr-asm-bb-exports.ll		diff \| blob \| history
llvm/test/CodeGen/X86/cvt16-2.ll		diff \| blob \| history
llvm/test/CodeGen/X86/cvt16.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fastmath-float-half-conversion.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fmf-flags.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fp-round.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fp-roundeven.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fp128-cast-strict.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fpclamptosat.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fpclamptosat_vec.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fptosi-sat-scalar.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fptoui-sat-scalar.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/freeze.ll		diff \| blob \| history
llvm/test/CodeGen/X86/frem.ll		diff \| blob \| history
llvm/test/CodeGen/X86/half-constrained.ll		diff \| blob \| history
llvm/test/CodeGen/X86/half.ll		diff \| blob \| history
llvm/test/CodeGen/X86/pr31088.ll		diff \| blob \| history
llvm/test/CodeGen/X86/pr38533.ll		diff \| blob \| history
llvm/test/CodeGen/X86/pr47000.ll		diff \| blob \| history
llvm/test/CodeGen/X86/scheduler-asm-moves.mir		diff \| blob \| history
llvm/test/CodeGen/X86/shuffle-extract-subvector.ll		diff \| blob \| history
llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16-fma.ll		diff \| blob \| history
llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll		diff \| blob \| history
llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir		diff \| blob \| history
llvm/test/CodeGen/X86/vec_fp_to_int.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-half-conversions.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll		diff \| blob \| history
llvm/test/MC/X86/x86_64-asm-match.s		diff \| blob \| history
mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_f16.mlir		diff \| blob \| history
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum_f16.mlir		diff \| blob \| history

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