[AMDGPU] Make vector superclasses allocatable
authorChristudasan Devadasan <Christudasan.Devadasan@amd.com>
Mon, 6 Sep 2021 03:40:10 +0000 (23:40 -0400)
committerChristudasan Devadasan <Christudasan.Devadasan@amd.com>
Fri, 26 Nov 2021 05:42:12 +0000 (00:42 -0500)
commit654c89d85a5108f2f04a8a748c44162e16260c7c
tree0f4f62ff349a50f8dac5330e7ec7e72dcc401921
parent7051aeef7a1ef609aaeea0bf87d90a2ec6340a37
[AMDGPU] Make vector superclasses allocatable

The combined vector register classes with both
VGPRs and AGPRs are currently unallocatable.
This patch turns them into allocatable as a
prerequisite to enable copy between VGPR and
AGPR registers during regalloc.

Also, added the missing AV register classes from
192b to 1024b.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D109300
13 files changed:
llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.h
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll