drm/i915: Use Write-Through cacheing for the display plane on Iris
authorChris Wilson <chris@chris-wilson.co.uk>
Thu, 8 Aug 2013 13:41:10 +0000 (14:41 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 22 Aug 2013 11:31:38 +0000 (13:31 +0200)
commit651d794fae9b79237aae1c97f8a9d9f3817bd31d
treea95018d3d8c8575f88ebc99af604564f90817927
parentea04cb31d506ac3f4fc3cefb1c50eb4f35ab37fd
drm/i915: Use Write-Through cacheing for the display plane on Iris

Haswell GT3e has the unique feature of supporting Write-Through cacheing
of objects within the eLLC/LLC. The purpose of this is to enable the display
plane to remain coherent whilst objects lie resident in the eLLC/LLC - so
that we, in theory, get the best of both worlds, perfect display and fast
access.

However, we still need to be careful as the CPU does not see the WT when
accessing the cache. In particular, this means that we need to flush the
cache lines after writing to an object through the CPU, and on
transitioning from a cached state to WT.

v2: Actually do the clflush on transition to WT, nagging by Ville.
v3: Flush the CPU cache after writes into WT objects.
v4: Rease onto LLC updates and report WT as "uncached" for
get_cache_level_ioctl to remain symmetric with set_cache_level_ioctl.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_gem_gtt.c
include/uapi/drm/i915_drm.h