powerpc/perf: Initialize power10 PMU registers in cpu setup routine
authorAthira Rajeev <atrajeev@linux.vnet.ibm.com>
Thu, 23 Jul 2020 07:32:37 +0000 (03:32 -0400)
committerMichael Ellerman <mpe@ellerman.id.au>
Sun, 26 Jul 2020 13:34:23 +0000 (23:34 +1000)
commit65156f2b1d9d5bf3fd0eac54b0a7fd515c92773c
treec716bcfb139aae54a306f0ec4b48d5554f58b467
parent84d8505ed1dafb2e62d49fca5e7aa7d96cfcec49
powerpc/perf: Initialize power10 PMU registers in cpu setup routine

Initialize Monitor Mode Control Register 3 (MMCR3)
SPR which is new in power10. For PowerISA v3.1, BHRB disable
is controlled via Monitor Mode Control Register A (MMCRA) bit,
namely "BHRB Recording Disable (BHRBRD)". This patch also initializes
MMCRA BHRBRD to disable BHRB feature at boot for power10.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Reviewed-by: Jordan Niethe <jniethe5@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1595489557-2047-1-git-send-email-atrajeev@linux.vnet.ibm.com
arch/powerpc/kernel/cpu_setup_power.S