[ARM] [FIX] Add missing f16 vector operations lowering
authorDiogo N. Sampaio <diogo.sampaio@arm.com>
Wed, 10 Apr 2019 13:28:06 +0000 (13:28 +0000)
committerDiogo N. Sampaio <diogo.sampaio@arm.com>
Wed, 10 Apr 2019 13:28:06 +0000 (13:28 +0000)
commit651463e4a8fe4ef29cdbe595ce32b1ffba6b2559
tree04ffec26758a292bb01b9c4145bd1d7bdaadb6dd
parent48e2eb0b27187776f4a033562828bc44f4dcf58d
[ARM] [FIX] Add missing f16 vector operations lowering

Summary:
Add missing <8xhalf> shufflevectors pattern, when using concat_vector dag node.
As well, allows <8xhalf> and <4xhalf> vldup1 operations.

These instructions are required for v8.2a fp16 lowering of vmul_n_f16, vmulq_n_f16 and vmulq_lane_f16 intrinsics.

Reviewers: olista01, pbarrio, LukeGeeson, efriedma

Reviewed By: efriedma

Subscribers: efriedma, javed.absar, kristof.beyls, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60319

llvm-svn: 358081
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/lib/Target/ARM/ARMInstrNEON.td
llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll