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[DAG] Limit (sext_in_reg (zero_extend_vector_inreg x)) to exact sign extension
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Sun, 21 Mar 2021 14:00:59 +0000 (14:00 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Sun, 21 Mar 2021 14:01:37 +0000 (14:01 +0000)
commit64c2641c895ab8d1d71c338294af8252969b7803
tree7fec9ad28f43f921edffcce56c702aa2f7b5e616tree | snapshot
parent8757616de38112a875e7e2ad38d851243ccb5d6bcommit | diff
[DAG] Limit (sext_in_reg (zero_extend_vector_inreg x)) to exact sign extension

As commented by @craig.topper on rG1ba5c550d418, we can't guarantee that we'll be extending zero bits, just sign bit. So, revert to the old code for zero_extend_vector_inreg cases.
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff | blob | history
Domain: System / Toolchain;