RISC-V: Add fence.tso instruction
authorPalmer Dabbelt <palmer@sifive.com>
Tue, 2 Oct 2018 15:26:32 +0000 (08:26 -0700)
committerPalmer Dabbelt <palmer@sifive.com>
Tue, 2 Oct 2018 15:26:32 +0000 (08:26 -0700)
commit64a336ac134ebd7f9452a7088e90e29551465251
tree43af5101dd733eaef5710e6ead74105397cc20ee
parentc1168a2f66553cd4730931cf59e3be8378a1a03f
RISC-V: Add fence.tso instruction

The RISC-V memory model has been ratified, and it includes an additional
fence: "fence.tso".  This pseudo instruction extends one of the
previously reserved full fence patterns to be less restrictive, and
therefor will execute correctly on all existing microarchitectures.
Thus there is no reason to allow this instruction to be disabled (or
unconverted to a full fence), so it's just unconditionally allowed.

I've added a test case for GAS to check that "fence.tso" correctly
assembles on rv32i-based targets.  I checked to see that "fence.tso"
appears in "gas.log", but that's the only testing I've done.

gas/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * testsuite/gas/riscv/fence-tso.d: New file.
        * testsuite/gas/riscv/fence-tso.s: Likewise.

include/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
        (MASK_FENCE_TSO): Likewise.

opcodes/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
gas/ChangeLog
gas/testsuite/gas/riscv/fence-tso.d [new file with mode: 0644]
gas/testsuite/gas/riscv/fence-tso.s [new file with mode: 0644]
include/ChangeLog
include/opcode/riscv-opc.h
opcodes/ChangeLog
opcodes/riscv-opc.c