drm/vc4: crtc: Add FIFO depth to vc4_crtc_data
authorMaxime Ripard <maxime@cerno.tech>
Thu, 3 Sep 2020 08:00:47 +0000 (10:00 +0200)
committerMaxime Ripard <maxime@cerno.tech>
Mon, 7 Sep 2020 16:02:57 +0000 (18:02 +0200)
commit649abf2f5d328a5a19824f712987f0a1de095332
tree753de0b8a9275588a907c380817ad2d5d20a34f3
parent87ebcd42fb7b8d1d3269007a621e41ae96a0077e
drm/vc4: crtc: Add FIFO depth to vc4_crtc_data

Not all pixelvalve FIFOs in vc5 have the same depth, so we need to add that
to our vc4_crtc_data structure to be able to compute the fill level
properly later on.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/7df3549c1bea9b0a27c784dc416bb9a831e4e18f.1599120059.git-series.maxime@cerno.tech
drivers/gpu/drm/vc4/vc4_crtc.c
drivers/gpu/drm/vc4/vc4_drv.h