AArch64: Add verifier for By elem Single and Double sized instructions.
authorTamar Christina <tamar.christina@arm.com>
Thu, 7 Feb 2019 16:55:23 +0000 (16:55 +0000)
committerTamar Christina <tamar.christina@arm.com>
Thu, 7 Feb 2019 16:56:35 +0000 (16:56 +0000)
commit6456d318aaa7ea35511dad1f2facf0fb984972e5
tree9ef3c078613f20160ad3e37d961e8da7dec79150
parentb2abe1bd8149dd9ad64432f620c3a034bf23a5fe
AArch64: Add verifier for By elem Single and Double sized instructions.

The AArch64 instruction set has cut-outs inside instructions encodings for
when a given encoding that would normally fall within the encoding space of
an instruction is instead undefined.

This updates the first few instructions FMLA, FMLA, FMUL and FMULX in the case
where sz:L == 11.

gas/ChangeLog:

PR binutils/23212
* testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test.
* testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test.

opcodes/ChangeLog:

PR binutils/23212
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
* aarch64-opc.c (verify_elem_sd): New.
(fields): Add FLD_sz entr.
* aarch64-tbl.h (_SIMD_INSN): New.
(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
fmulx scalar and vector by element isns.
gas/ChangeLog
gas/testsuite/gas/aarch64/undefined_by_elem_sz_l.d [new file with mode: 0644]
gas/testsuite/gas/aarch64/undefined_by_elem_sz_l.s [new file with mode: 0644]
opcodes/ChangeLog
opcodes/aarch64-opc.c
opcodes/aarch64-opc.h
opcodes/aarch64-tbl.h