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[compiler-rt] [builtins] [AArch64] Add missing AArch64 data synchronization barrier...
authorStephen Hines <srhines@google.com>
Fri, 11 Jun 2021 09:07:59 +0000 (02:07 -0700)
committerStephen Hines <srhines@google.com>
Fri, 11 Jun 2021 09:13:48 +0000 (02:13 -0700)
commit6455418d3d2a2de1a8251cc2ccf2e87b9ae3112d
tree046a97171c96bc8076432a2e835e7adb0d76472ctree | snapshot
parent47d138c93992f779a5dd0810b0e7402e043df61dcommit | diff
[compiler-rt] [builtins] [AArch64] Add missing AArch64 data synchronization barrier (dsb) to __clear_cache

https://developer.arm.com/documentation/den0024/a/Caches/Cache-maintenance
covers how to properly clear caches on AArch64, and the builtin
implementation was missing a `dsb ish` after clearing the icache for the
selected range.

Reviewed By: kristof.beyls

Differential Revision: https://reviews.llvm.org/D104094
compiler-rt/lib/builtins/clear_cache.c diff | blob | history
Domain: System / Toolchain;