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(parent: 2ad4c3c) | patch
AMDGPU/GlobalISel: Widen s1 SGPR constants during regbankselect
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 27 Dec 2022 15:37:52 +0000 (10:37 -0500)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 10 Jan 2023 19:45:23 +0000 (14:45 -0500)
commit6454391b3111993f277fb2570d28f59699b7dae2
tree46b996db2b90537f3ef86321642d8e4fa54e01d7tree | snapshot
parent2ad4c3c88d884684a3efb42181e87fe305df51bdcommit | diff
AMDGPU/GlobalISel: Widen s1 SGPR constants during regbankselect

To unambiguously interpret these as 32-bit SGPRs, we need to widen
these to s32. This was selecting to a copy from a 64-bit SGPR to a
32-bit SGPR for wave64.
13 files changed:
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/br-constant-invalid-sgpr-copy.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll diff | blob | history
Domain: System / Toolchain;