AMDGPU: Disallow exec as SMEM instruction operand
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 29 Nov 2016 19:39:53 +0000 (19:39 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 29 Nov 2016 19:39:53 +0000 (19:39 +0000)
commit640c44b8931cacab55995c7e5b07623e0a59f4a3
treed5ee18b1f4a7ca0fc0bcf738eeef005a168f6619
parentcdad316cc2a990b2e6e5f0602aaff7a1dbc7e7e4
AMDGPU: Disallow exec as SMEM instruction operand

This is not in the list of valid inputs for the encoding.
When spilling, copies from exec can be folded directly
into the spill instruction which results in broken
stores.

This only fixes the operand constraints, more codegen
work is required to avoid emitting the invalid
spills.

This sort of breaks the dbg.value test. Because the
register class of the s_load_dwordx2 changes, there
is a copy to SReg_64, and the copy is the operand
of dbg_value. The copy is later dead, and removed
from the dbg_value.

llvm-svn: 288191
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
llvm/lib/Target/AMDGPU/SMInstructions.td
llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
llvm/test/CodeGen/AMDGPU/spill-m0.ll
llvm/test/MC/AMDGPU/smem-err.s [new file with mode: 0644]