ch_ktls: Correction in middle record handling
authorRohit Maheshwari <rohitm@chelsio.com>
Mon, 9 Nov 2020 10:51:37 +0000 (16:21 +0530)
committerJakub Kicinski <kuba@kernel.org>
Thu, 12 Nov 2020 00:30:37 +0000 (16:30 -0800)
commit63ee4591fa2f97dc08ce37514f214fc0430e9dc3
treec74b7d100a7ad8769185af121f5cefd28168b581
parent83deb094dd5c636a790da3914008570c9fd1693f
ch_ktls: Correction in middle record handling

If a record starts in middle, reset TCB UNA so that we could
avoid sending out extra packet which is needed to make it 16
byte aligned to start AES CTR.
Check also considers prev_seq, which should be what is
actually sent, not the skb data length.
Avoid updating partial TAG to HW at any point of time, that's
why we need to check if remaining part is smaller than TAG
size, then reset TX_MAX to be TAG starting sequence number.

Fixes: 5a4b9fe7fece ("cxgb4/chcr: complete record tx handling")
Signed-off-by: Rohit Maheshwari <rohitm@chelsio.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/chelsio/inline_crypto/ch_ktls/chcr_ktls.c