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(parent: c85c24d) | patch
hdmitx: optimise the clock divider
authorZongdong Jiao <zongdong.jiao@amlogic.com>
Fri, 2 Mar 2018 10:24:07 +0000 (18:24 +0800)
committerJianxin Pan <jianxin.pan@amlogic.com>
Tue, 6 Mar 2018 03:39:08 +0000 (19:39 -0800)
commit63d9a286603f9ebc19d0fb98e5c9f88ce52bd70e
tree7f375b10daca28b6a8dde79f8f4884b08c0dc8e0tree | snapshot
parentc85c24ded14fa5a114ba25a987fbc698a70f411bcommit | diff
hdmitx: optimise the clock divider

PD#156734: optimise the clock divider of VID_PLL_DIV
This is a bridge of analog signal and digital signal module.
With VCO output 4.455Gbps/2160p60hzY420 12bits mode and the
ENCP needs 594MHz, there should divide half to reduce the
risk of HHI_VID_PLL_CLK_DIV.

Change-Id: If6965d64df1aa4b7cb4a8dd66847db3d5d17aea7
Signed-off-by: Zongdong Jiao <zongdong.jiao@amlogic.com>
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c diff | blob | history
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.h diff | blob | history
Domain: System / Kernel;