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(parent: 9e98c67) | patch
clk: imx5: Fix i.MX50 mainbus clock registers
authorJonathan Neuschäfer <j.neuschaefer@gmx.net>
Tue, 26 Mar 2019 18:22:57 +0000 (19:22 +0100)
committerShawn Guo <shawnguo@kernel.org>
Wed, 3 Apr 2019 09:09:50 +0000 (16:09 +0700)
commit639eb92531166a17bdb459437fbadf97459c5370
treee8b93f27b6541399ba9b8023c405f84a58c749e7tree | snapshot
parent9e98c678c2d6ae3a17cb2de55d17f69dddaa231bcommit | diff
clk: imx5: Fix i.MX50 mainbus clock registers

i.MX50 does not have a periph_apm clock. Instead, the main bus clock
(a.k.a. periph_clk) comes directly from a MUX between pll1_sw, pll2_sw,
pll3_sw, and lp_apm.

Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
drivers/clk/imx/clk-imx51-imx53.c diff | blob | history
Domain: System / Kernel;